The present invention relates generally to data processors, and more specifically the invention pertains to an arrangement which provides for the on-board programming of an EEPROM memory.
Most processors use programmable read only memories (PROMs) to store program code. To avoid the necessity of removing the PROMs for programming, it is very desirable to program the PROMs while they are on-board. While electrically erasable PROMs (EEPROMs) have simplified some of the difficulties, adding PROM programming capability usually increases the complexity of the design, adds components, and uses additional board space.
The electrically erasable programmable read only memory (EEPROM) is a field-programmable read only memory in which cells may be erased electrically and each cell may be reprogrammed electrically. The number of times the EEPROM can be reprogrammed (write/erase cycles) ranges from 10 times to 10.sup.6 times.
Existing systems either add specialized circuitry for on board programming or tend to remove, reprogram, and replace EEPROMs in data processing systems when required by using a separate specialized program system. However, in general, it seems wasteful to have to add specialized circuitry to accommodate programming when there is a powerful processor already present. If the processor could be configured to be not only the main processor running out of the EEPROM, but also an intelligent EEPROM programmer that could load the EEPROM, then the problem of on-board programming would be simplified.
The task of providing a dual function data processing system that performs its main task and can program EEPROM chip elements is alleviated, to some extent, by the systems described in the following U.S. patents, the disclosures of which are incorporated herein by reference:
U.S. Pat. No. 4,156,926 issued to Hartman; PA1 U.S. Pat. No. 4,712,190 issued to Guglielimi et al; PA1 U.S. Pat. No. 4,718,037 issued to Thaden; PA1 U.S. Pat. No. 4,752,871 issued to Sparks et al; and PA1 U.S. Pat. No. 4,794,558 issued to Thompson.
Sparks et al disclose a single chip microcomputer comprising at least two separate and independent EEPROMs on board which may be independently programmed, erased and read. The split EEPROM provides versatility in allowing one part of the EEPROM to be programmed while the program stored in the other part of the EEPROM may be read and utilized.
Thompson is concerned with a single-chip microcomputer with a CPU which has an EEPROM control register loadable under the control of a computer program stored in an external memory. The microcomputer has the capability of utilizing its own CPU to program the EEPROM.
In Thaden a microprocessor system includes an internal memory and further includes an electrically programmable read-only memory for the storage of data and commands which define operations on the data. Guglielmi et al describe a self-timed random access memory circuit designed on a single monolithic integrated circuit chip. In Hartman a PROM programmer programs an array of PROMs mounted on a circuit board.
As discussed by the above-cited references, the provision of data processing systems with built-in systems level EEPROM programming abilities is an ongoing need to which many technical solutions are being applied. The present invention is intended to satisfy that need.